1. Field of the Invention
The present invention relates to a method of converting a data set for use with a digital model into an expanded data set for use with an analogue model.
2. Discussion of the Related Art
In the past during mixed signal IC device or xe2x80x98chipxe2x80x99 development, testing departments have had to wait until a device has been reduced to silicon before functional tests can be performed. In view of the increase in the general requirements for mixed signal (using digital and analogue signals) chips and their shrinking product shelf life, the need to reduce development time has risen accordingly. By testing IC device designs prior to reduction to silicon overall development times can be reduced considerably. This means that a device can be brought to market more quickly.
A number of test simulators are known which allow test departments to test how a device will function as soon as a preliminary design is completed. This can be prior to the reduction to silicon of the device.
One type of test simulator is an analog simulator which may be used for non-linear DC, non-linear transient and linear AC analysis. SPICE is an example of an industry standard general-purpose analog circuit simulator. A development of the SPICE simulator is the ELDO simulator which provides the functionality, performance and accuracy of SPICE-level simulation along with improved algorithms which allow more complex circuits to be simulated and also provides a mixed signal simulation capability.
Analog simulators, as the name suggests, allow simulation of a hardware cell being tested at the analog signal level. The simulator provides performance results through the whole range of analog input signals and allows for voltage sweeps. In other words, the cell is tested over a wide range of voltage values, the voltage values being for example applied as inputs. As a result analog simulators provide very accurate descriptions of the designed device operation. However simulation times can be prohibitively protracted especially when a design comprises many thousands or hundreds of thousands of cells to be simulated.
As a solution to the task of describing circuits of such large scale, digital simulators have been developed. Numerous digital simulators have been developed to model the behaviour of circuitry described using a hardware description language (HDL). HDL is a programming language which has been designed and optimised for simulating and thereby describing behaviour of digital circuitry. HDL allows electrical aspects of circuit behaviour to be precisely described. However since only digital signals (which have one of two states) are simulated simulation time scales are much reduced. Additionally, only changes of logic level trigger an evaluation of the effect. A specific example of HDL is the very high speed integrated circuit HDL known as VHDL.
HDL models typically provide a behavioural description of the circuitry of the designed device which can be synthesised into a net list which includes circuit diagrams of the device saved in textual form. In other words, the circuitry of the device is broken down into cells or small circuit portions, each of which has a known behaviour. These cells or small circuit portions are listed in the net list. Operation of the device is simulated by stimulating the net list by the application of a test bench. Test benches are HDL descriptions of circuit stimulus. The outputs of the cell in response to stimulus are compared with expected outputs to verify the behaviour of a circuit over time. The verification results may be analysed to establish how the circuit has functioned.
A problem is that whilst various cells whose operation has an analog type behaviour are modelled as a VHDL behavioural description or a net list of transistors there is no real verification between the cells response in a true analog simulator such as ELDO. As the cells are analogue cells, the analogue simulator would provide a more accurate reflection of the behaviour of the cell. Certainly no such real verification is achieved by automatic means but it is rather a further requirement for the model writer. As such it can be a further source of error in a design. This problem also applies to digital circuits as they can be regarded as analogue cells with very high gains so that the outputs tend to be rail to rail.
VHDL supports many abstract data types which are used to described different signal strengths or commonly used simulation conditions such as unknowns and high-impedance conditions. These non-standard data types have been adopted by the IEEE as standard 1164. Such data types are not applicable to analog simulators which require true analog signals rather than abstract data types.
It is an aim of embodiments of the present invention to at least partly mitigate the above problems.
According to a first aspect of the present invention there is provided a method of converting a data set for use with a digital model of a hardware cell into an expanded data set for use with an analogue model of the hardware cell comprising the steps of determining the signal required to drive one or more pins of said analogue model by analysing whether the signals used in said digital model are in a first category or a second category, said first category containing relatively simple signals and said second category containing relatively complex signals; and providing the signal required for the one or more pins in the analogue model in dependence on said analysis.
The digital model may be an HDL model, for example a VHDL model.
A third category may be provided, said third category containing signals which have a complexity between that of the first and second categories. In the third category, a pin is driven with two levels of equal drive. These levels may be 0 and 1. For a signal in the first category, the same stimulus is applied to a pin, in preferred embodiments of the present invention.
Preferably, if a signal to be applied is in the first category, the pin is tied to one of the supplies.
Preferably, in the second category, complex stimuli are used to generate the signals to be applied.
Preferably the method further comprises the step of generating the second category of signals by comparing the value of each input signal with a plurality of entries in the look-up table and selecting an entry from said look-up table corresponding to the value for each input signal, and responsive to the or each selected entry selectively configuring control circuitry to provide an output signal, said signal being arranged to be applied to a corresponding input of the analogue model. It should be appreciated that this technique can be used with signals in the first and/or second category. It should be appreciated that the look-up table can be replaced by any other suitable mechanism such as an algorithm.
Preferably, the method further comprises the step of for each pin identifying an entry for each successive input signal on the pin, thereby providing a succession of values. Preferably, a binary representation of each entry is provided for each pin and an OR logic operation is provided on the binary representations, the result of which may provide a reference output which is used to control the signal applied to the pin.
For each signal to be applied, an associated voltage level to be applied to the analogue model may be determined and a voltage source responsive to the determined voltage level may be selected. Preferably, for each signal to be applied a drive strength is determined and the voltage is applied to the pin via a resistive element if required. Some input signals may require the use of a resistive element, others may not. The resistive element can be a resistor or any other suitable device. It should be appreciated that in the context of the preferred embodiment of the present invention, this resistive element will be implemented in software.
The selected voltage source may be connected to switching apparatus which is selectively operable to connect the selected voltage source to the resistive element, the switching apparatus being responsive to control signals. Preferably, one or more control signals are applied to the switching apparatus for one or more different signals to be applied.
According to a second aspect of the present invention there is provided a system for converting a data set for use with the digital model of the hardware cell into an expanded set for use with an analogue model of the hardware cell, said system comprising means for determining the signal required to drive one or more pins of the analogue model by analysing whether the signals used in the digital model are in a first category or a second category, the first category containing relatively simple signals and the second category containing relatively complex signals; and means for providing the signal required for the one or more pins in the analogue model in dependence on the analysis carried out by said determining means.